Tuesday, April 2, 2013

Optimizing the Tracking Pre-Regulator Design

In my last post I investigated a bit into a novel tracking pre-regulator design by John Barnes (I originally heard of this design in Dave Jones' EEVBlog #329 video). I had modeled mathematically the system rather than using SPICE simulation software as Dave did to play with the design and came up with a fairly nice model for figuring out what parameters to use. This is just a slight update as I investigated the design a bit further. In this post I'm going to present a novel way to make the transistor gain error nearly negligible.

So how do we accomplish this? It's actually quite easy, just set $$R_3 = R_1$$. Why does this work? Recall from my last post the equation for calculating pre-regulation offset:

$V_{reg} - V_{set} = \frac{\beta R_1 V_{FB}}{(1 + \beta) R_2} + \frac{R_3 V_{FB}}{R_2 \beta} + V_{EB}$

Let's see what happens if $$R_3 = R_1$$.

$V_{reg} - V_{set} = \frac{\beta R_1 V_{FB}}{(1 + \beta) R_2} + \frac{R_1 V_{FB}}{R_2 \beta} + V_{EB}\\ V_{reg} - V_{set} = \frac{R_1 V_{FB}}{R_2} \left ( \frac{\beta}{(1 + \beta)} + \frac{1}{\beta} \right ) + V_{EB}\\ V_{reg} - V_{set} = \frac{R_1 V_{FB}}{R_2} \left ( \frac{\beta^2 + \beta + 1}{\beta^2 + \beta} \right ) + V_{EB}$

Hello, look at the terms with $$\beta$$'s. As the transistor gain gets larger the change in pre-regulation offset drops off extremely rapidly. Let's plot the error:

Even as the gain approaches 10 (typically accepted as fully saturated, in which case this model fails to be accurate), the error is under 0.5%. For more practical gain values, (say $$\beta > 50$$) the error drops below 0.01%. Not bad for just matching two resistors.