Tuesday, March 26, 2013

Tracking Pre-Regulator Design Analysis


I was watching a rather interesting EEVBlog video where Dave Jones showed a tracking pre-regulator design someone named "John Barnes" sent him (hopefully I got that right). Unlike his first video where he took Linear Technologies example circuit which uses the threshold voltage of a MOSFET to set the pre-regulator voltage, the new design uses a PNP transistor and resistors to calibrate the pre-regulator voltage. This design has several advantages over the MOSFET design. The main big one is that the threshold voltage can be set indepedendant of the specific component parts used, where-as the MOSFET design was highly dependant on the exact part used. Additionally, the ability to find the specific MOSFET with the correct threshold was unlikely. Dave did say you could compensate for this by adding diodes, but really this is a poor design in my opinion and he seemed to agree. Dave did some spice simulations with some actual parts and was able to parametrically evaluate what resistor values to use for a given target pre-regulator voltage. This is great if you have the available parts in your simulation software, but I wondered if I couldn't arrive at the solution using some math so I could design with any components I wanted. I also was curious as to why the thing worked to begin with, which the simulation software doesn't give too much indication towards.

H-parameter Modeling

Figure 1 shows the key representative components in question. The pre-regulator provides some input voltage \(V_{reg}\). For the LT3080, the output voltage is directly correlated to the set voltage, i.e. \(V_{out} = V_{set}\). Like Dave's design, I'm going to assume that this pin is being driven from a low-impedance source (such as a op-amp). The pre-regulator takes a feedback voltage \(V_{FB}\) and compares it to an internal reference \(V_{ref}\). If the feedback voltage is higher than the internal target voltage, the pre-regulator will try to increase the pre-regulated voltage. Likewise, if the feedback voltage is under the internal reference the pre-regulator will try to decrease the pre-regulation voltage. When the feedback voltage equals the internal reference, we're golden and the pre-regulator voltage is set exactly where we want it to be. The arrows represent the assumptions of current flow I'm making.

Figure 1. Representative model of the circuit

For this analysis I'm going to assume that we are in the "steady state" region where the pre-regulator voltage is where we want it to be. The first step is to make an assumption about the transistor's state. Let's assume that the transistor is in an active state.

Let's go ahead and write out the relavent equations. I'm assuming that the h-parameter model is valid.

\[ i_E = \frac{V_{reg} - V_E}{R1}\\ i_C = \frac{V_{FB}}{R_2}\\ i_B = \frac{V_B - V_{set}}{R_3}\\ V_E = V_{BE} + V_B\\ i_B = \frac{i_C}{\beta}\\ i_E = i_C + i_B \]

We need to pick what values we want to fix and which ones we want to solve for. For my first test I'm going to solve for R1.

\[ R_1 = \frac{(1 + \beta)}{\beta^2 V_{FB}} \cdot \left( \beta R_2 (V_{reg} - V_{set} - V_{EB}) - R_3 V_{fb} \right) \]

There are a few things we can pick out from this equation. The first one is that values of \(R_3\) won't significantly affect the output, assuming it's roughly in the same order of magnitude as \(R_2\). The second is dependency of the output based off of different transistor gains. The only term which is significantly affected by \(\beta\) is the term with \(R_3\), which we've already meantioned isn't too significant. The larger the transistor gain, the less significant \(R_3\) is. Let's re-arrange the above equation and solve for \(V_{reg} - V_{set}\). This will allow us to observe how various parameter tolerances would effect the pre-regulation voltage rise above the final output voltage.

\[ V_{reg} - V_{set} = \frac{\beta R_1 V_{FB}}{(1 + \beta) R_2} + \frac{R_3 V_{FB}}{R_2 \beta} + V_{EB} \]

From this equation we can tell that the majority of the error will come from \(R_1\) and \(R_2\) as well as from \(V_{EB}\). \(V_{EB}\) is mostly affected by temperature while \(R_1\) and \(R_2\) will be significantly affected by manufacturing tolerances.

We can verify these claims by looking at some plots. Figure 2 shows the change in pre-regulation offset vs. the resistor tolerances. \(R_2\) and \(R_3\) are both set to nominal \(10k \Omega\) and \(R_1\) is set to a nominal \(1k \Omega\). I'm assuming \(\beta = 100\), \(V_{fb} = 0.7V\), and \(V_{EB} = 0.65V\). This configuration will result in a nominal pre-regulation offset of 0.72315V.

Figure 2. Pre-regulation offset error vs. Resistances

Figure 3 shows the pre-regulation offset vs. \(V_{EB}\). The same parameters are chosen as from figure 2.

Figure 3. Pre-regulation offset vs. Veb

Figure 4 shows the pre-regulation offset vs. \(\beta\). The same parameters are chosen as from figure 2.

Figure 4. Pre-regulation offset error vs. \(\beta\)

With larger offsets, the error balance influence will change. The influence of \(V_{EB}\) will be reduced, and likewise the error contribution from resistance tolerances will increase. What-ever the case, the error is fairly small.

Checking Transistor State Assumptions

Earlier we made the assumption that the transistor was in the active region. We need to check to make sure this assumption is correct. To be in the active region, the emitter/base pair must be forward-biased saturated and the collector/base pair must be in reverse bias. By design \(V_{set} > V_{fb}\), otherwise the pre-regulator is the primary limiting device. This implicitly means that the collector/base pair is always reverse-biased.

There's the possibility that \(V_{E} < V_{B} + V_{EB}\). In this state the transistor is effectively switched off. However, that would imply that that the pre-regulator feedback pin will be pulled down to ground, causing the pre-regulator to try to compensate accordingly by increasing \(V_{reg}\), until the emitter/base pair are forward biased saturated again and the transistor re-enters the active region, or reaches a maximum possible output and the system is limited by the pre-regulator. So in steady state we are either violating the abilities of the pre-regulator, or the system will auto-stabilize the transistor in the active region.

Simplifying the Calculations

In my calculations above I did not assume that base current is insignificant. This resulted in a rather complex calculation. If we can make this assumption, the calculation will be simplified significantly. So the question becomes under what conditions this assumption is valid.

First, let's analyze what approximations we can make if the base current is assumed to be insignificant. That means that the base voltage is exactly the set voltage. Additionally, this means that \(i_E = i_C\). To validate this assumption, we need to check that \(i_C >> i_B\). That's easy to do, since the two are related by \(\beta\) since we're in the active region. If \(\beta\) is sufficiently large, our error will be small. What limit is acceptable is up to you, though I would argue that a value of 100 or larger would be sufficient.

To check that base voltage is close to the set voltage, let's analyze the voltage drop across \(R_3\).

\[ i_B = \frac{i_C}{\beta} = \frac{V_{FB}}{R_2 \beta}\\ \frac{V_B - V_{set}}{V_{set}}= \frac{i_B R_3}{V_{set}} = \frac{V_{FB} R_3}{R_2 \beta V_{set}} \]

As explained above, \(V_{set} > V_{FB}\). As long as this ratio is significantly small, we can safely assume base current is negligible.

Here are the calculations assuming a negligible base current:

\[ R_1 = \frac{R_2 (V_{reg} - V_{EB} - V_{set})}{V_{FB}}\\ V_{reg} = \frac{R_1}{R_2} V_{FB} + V_{EB} + V_{set} \]


So there we go. This design works by using a PNP transistor in its active region, and works quite well with a wide variety of component choices and design goals. We have 2 different ways to calculate the various parameters, one which is more accurate and the other which is quite simple. The last concluding remark is that these calculations are valid only if the h-parameter model is valid. For even better accuracy, consider using the Ebers-Moll model. This model is more accurate for large-signals (behaviour is non-linear). I haven't validated that this design can be sufficiently approximated with a linear model, though more than likely it is.

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