In my last post I investigated a bit into a novel tracking pre-regulator design by John Barnes (I originally heard of this design in Dave Jones' EEVBlog #329 video). I had modeled mathematically the system rather than using SPICE simulation software as Dave did to play with the design and came up with a fairly nice model for figuring out what parameters to use. This is just a slight update as I investigated the design a bit further. In this post I'm going to present a novel way to make the transistor gain error nearly negligible.
So how do we accomplish this? It's actually quite easy, just set R3=R1. Why does this work? Recall from my last post the equation for calculating pre-regulation offset:
Vreg−Vset=βR1VFB(1+β)R2+R3VFBR2β+VEBLet's see what happens if R3=R1.
Vreg−Vset=βR1VFB(1+β)R2+R1VFBR2β+VEBVreg−Vset=R1VFBR2(β(1+β)+1β)+VEBVreg−Vset=R1VFBR2(β2+β+1β2+β)+VEBHello, look at the terms with β's. As the transistor gain gets larger the change in pre-regulation offset drops off extremely rapidly. Let's plot the error:
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Even as the gain approaches 10 (typically accepted as fully saturated, in which case this model fails to be accurate), the error is under 0.5%. For more practical gain values, (say β>50) the error drops below 0.01%. Not bad for just matching two resistors.
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